The present invention relates to an impedance detection circuit that detects an impedance of a circuit connected to a signal line or a similar circuit, and to a method of adjusting a parasitic impedance associated with the impedance detection circuit.
As electronic systems have become more sophisticated in recent years, circuits to detect impedance values such as capacitance sensors have been increasingly used in such electronic systems. Since such impedance detection circuits are installed in various devices, it is desirable that they are small in size and easily adjusted. Further, those impedance detection circuits need to be capable of accurately detecting impedance values regardless of the external environment.
An example of a circuit to detect the impedance of a capacitive element has been proposed (Japanese Unexamined Patent Application Publication No. 2002-350477). FIG. 4 shows a circuit diagram schematically showing a configuration of a capacitance-voltage conversion device (impedance detection circuit) in related art. This impedance detection circuit 300 is explained hereinafter with reference to FIG. 4. The impedance detection circuit 300 operates so that an unknown capacitance Cs of a capacity 30 to be measured is converted into a corresponding voltage (i.e., voltage in proportion to the capacitance Cs). This impedance detection circuit 300 is composed of a detection circuit 31, a phase compensation circuit 32, an amplitude compensation circuit 33, a subtraction circuit 34, and an AC (alternating-current) signal generator 35.
The detection circuit 31 detects the capacitance Cs of the capacity 30 to be measured. The detection circuit 31 includes an operational amplifier 41. The operational amplifier 41 is an amplifier whose voltage gain is extremely larger than the closed-loop gain and thereby appears to be almost infinity. A feedback resistor 42 having a resistance value Rf1 is connected between the output terminal and the inverting input terminal (−) of the operational amplifier 41. In this way, a negative feedback is applied to the operational amplifier 41. A driving signal output from the AC signal generator 35 is applied to the non-inverting input terminal (+) of the operational amplifier 41. The inverting input terminal (−) of the operational amplifier 41 is also connected to one end of the capacity 30 to be measured through a signal line 43. A constant DC (direct-current) bias Vh is applied to the other end of the capacity 30 to be measured.
To prevent any unnecessary signal such as external noises from entering the signal line 43, the signal line 43 is enclosed with a shield line 44. The shield line 44 is not connected to the ground, but is connected to the non inverting input terminal (+) of the operational amplifier 41.
Note that the symbol Cp in FIG. 4 represents a parasitic capacitance occurring in the unshielded part of the signal line 43, i.e., the part of the signal line 43 that is unavoidably exposed. There is a possibility that an AC signal in the surrounding area could be applied to the inverting input terminal (−) of the operational amplifier 41 through this parasitic capacitance Cp.
As described above, the negative feedback is applied to the operational amplifier 41 through the feedback resistor 42. Further, the operational amplifier 41 is an amplifier whose voltage gain is extremely larger than the closed-loop gain, and thus the voltage gain appears to be almost infinity. Therefore, both of the input terminals of the operational amplifier 41 are in an imaginary short-circuit state. That is, the voltage difference between the inverting input terminal (−) and the non-inverting input terminal (+) of the operational amplifier 41 is substantially zero. Therefore, the signal line 43 and the shield line 44 are at the same potential (i.e., the same voltage). In this way, it is possible to cancel out the stray capacitance occurring between the signal line 43 and the shield line 44. This feature holds regardless of the length of the signal line 43. Further, it also holds regardless of whether or not the signal line 43 is moved, bent, or folded.
The phase compensation circuit 32 is a circuit that corrects the phase of a driving signal output from the AC signal generator 35. The phase compensation circuit 32 includes an operational amplifier 51. A feedback resistor 52 having a resistance value R1 is connected between the output terminal and the inverting input terminal (−) of the operational amplifier 51. A driving signal output from the AC signal generator 35 is applied to the inverting input terminal (−) of the operational amplifier 51 through a resistor 53 having a resistance value R1. Further, this driving signal is also applied to the non-inverting input terminal (+) of the operational amplifier 51 through a variable resistor 54 having a resistance value Ri2. The non-inverting input terminal (+) of the operational amplifier 51 is connected to the ground through a capacitor 55 having a capacitance C2.
The amplitude compensation circuit 33 is a circuit to correct the amplitude of the driving signal output from the AC signal generator 35. The amplitude compensation circuit 33 includes an operational amplifier 61. A feedback resistor 62 having a resistance value Rf3 is connected between the output terminal and the inverting input terminal (−) of the operational amplifier 61. The output voltage of the phase compensation circuit 32, i.e., the output V2 of the operational amplifier 51 is applied to the inverting input terminal (−) of the operational amplifier 61 through a resistor 63 having a resistance value Ri3. The non-inverting input terminal (+) of the operational amplifier 61 is connected to the ground. Further, the output V3 of the operational amplifier 61 is connected to the inverting input terminal (−) of the operational amplifier 41 through a resistor 45 having a resistance value Ri1. Note that the current generated by the capacitance Cs and the parasitic capacitance Cp flows toward the feedback resistor 42. In this state, an adjusted current flows from the output of the amplitude compensation circuit 33 into the feedback resistor 42 through the resistor 45 so that the part of the current that is caused by the additional parasitic capacitance Cp is cancelled out.
The subtraction circuit 34 is a circuit to subtract the output of the AC signal generator 35 from the output of the detection circuit 31. The subtraction circuit 34 includes an operational amplifier 71. A feedback resistor 72 having a resistance value R1 is connected between the output terminal and the inverting input terminal (−) of the operational amplifier 71. The output voltage of the detection circuit 31, i.e., the output V1 of the operational amplifier 41 is applied to the inverting input terminal (−) of the operational amplifier 71 through a resistor 73 having a resistance value R1. The output of the AC signal generator 35 is applied to the non-inverting input terminal (+) of the operational amplifier 71 through a resistor 74 having a resistance value R1. The DC bias Vh is applied to the non-inverting input terminal (+) of the operational amplifier 71 through a resistor 75 having a resistance value R1.
The driving signal output from the AC signal generator 35 is the sum of an AC signal Vdv and the DC bias Vh. However, the DC bias Vh may be set to zero. The operation of the impedance detection circuit 300 shown in FIG. 4 is explained hereinafter. The signal line 43, which connects the inverting input terminal of the operational amplifier 41 of the detection circuit 31 to one of the electrodes forming the capacity 30 to be measured, is enclosed with and shielded by the shield line 44. However, even when the capacity 30 to be measured is not connected, the phase of the output of the impedance detection circuit 300, i.e., the phase of the output Vout of the operational amplifier 71 is shifted from the phase of the AC signal Vdv though the amount of the shift is small. This is because the parasitic capacitance Cp, which occurs in the part of the signal line 43 that is unavoidably exposed due to the wiring connection and the like, remains.
Therefore, to cancel out the phase shift like this, the phase and the amplitude of the AC signal Vdv are adjusted by the phase compensation circuit 32 and the amplitude compensation circuit 33 respectively. In this way, the adjusted signal, i.e., the output V3 of the operational amplifier 61 is fed back to the inverting input terminal of the operational amplifier 41 of the detection circuit 31 through the resistor 45.
In the following explanation, the angular frequency of the AC signal Vdv is represented by “ω”. The output V2 of the phase compensation circuit 32 is expressed by Equation (1) shown below.
                              V          2                =                                                            1                -                                  j                  ⁢                                                                          ⁢                  ω                  ⁢                                                                          ⁢                                      C                    2                                    ⁢                                      R                                          i                      ⁢                                                                                          ⁢                      2                                                                                                  1                +                                  j                  ⁢                                                                          ⁢                  ω                  ⁢                                                                          ⁢                                      C                    2                                    ⁢                                      R                                          i                      ⁢                                                                                          ⁢                      2                                                                                            ⁢                          V              dv                                +                      V            h                                              (        1        )            
The output V3 of the amplitude compensation circuit 33 is expressed by Equation (2) shown below.
                              V          3                =                              -                                                            R                                      f                    ⁢                                                                                  ⁢                    3                                                  ⁢                                                                                              R                                  i                  ⁢                                                                          ⁢                  3                                                              ⁢                                    1              -                              j                ⁢                                                                  ⁢                ω                ⁢                                                                  ⁢                                  C                  2                                ⁢                                  R                                      i                    ⁢                                                                                  ⁢                    2                                                                                      1              +                              j                ⁢                                                                  ⁢                ω                ⁢                                                                  ⁢                                  C                  2                                ⁢                                  R                                                            i                      ⁢                                                                                          ⁢                      2                                        ⁢                                                                                                                                              ⁢                      (                                          V                dv                            +                              V                h                                      )                                              (        2        )            
The output V1 of the detection circuit 31 is expressed by Equation (3) shown below.
                              V          1                =                              j            ⁢                                                  ⁢            ω            ⁢                                                  ⁢                          C              s                        ⁢                          R                              f                ⁢                                                                  ⁢                1                                      ⁢                          V                              d                ⁢                                                                  ⁢                v                                              +                      j            ⁢                                                  ⁢            ω            ⁢                                                  ⁢                          C              p                        ⁢                                          R                                  f                  ⁢                                                                          ⁢                  1                                            ⁡                              (                                                      V                    dv                                    +                                      V                    h                                                  )                                              +                                    {                              1                +                                                      R                                          f                      ⁢                                                                                          ⁢                      1                                                                            R                                          i                      ⁢                                                                                          ⁢                      1                                                                      +                                                                            R                                              f                        ⁢                                                                                                  ⁢                        1                                                                                    R                                              i                        ⁢                                                                                                  ⁢                        1                                                                              ⁢                                                            R                                              f                        ⁢                                                                                                  ⁢                        3                                                                                    R                                              i                        ⁢                                                                                                  ⁢                        3                                                                              ⁢                                                            1                      -                                              j                        ⁢                                                                                                  ⁢                        ω                        ⁢                                                                                                  ⁢                                                  C                          2                                                ⁢                                                  R                                                      i                            ⁢                                                                                                                  ⁢                            2                                                                                                                                      1                      +                                              j                        ⁢                                                                                                  ⁢                        ω                        ⁢                                                                                                  ⁢                                                  C                          2                                                ⁢                                                  R                                                      i                            ⁢                                                                                                                  ⁢                            2                                                                                                                                                          }                        ⁢                          (                                                V                  dv                                +                                  V                  h                                            )                                                          (        3        )            
The output Vout of the subtraction circuit 34 is expressed by Equation (4) shown below.
                                                                        V                out                            =                            ⁢                                                                    -                    j                                    ⁢                                                                          ⁢                  ω                  ⁢                                                                          ⁢                                      C                    s                                    ⁢                                      R                                          f                      ⁢                                                                                          ⁢                      1                                                        ⁢                                      V                    dv                                                  -                                  j                  ⁢                                                                          ⁢                  ω                  ⁢                                                                          ⁢                                      C                    p                                    ⁢                                      R                                          f                      ⁢                                                                                          ⁢                      1                                                        ⁢                                      (                                                                  V                        dv                                            +                                              V                        h                                                              )                                                  -                                                                                                      ⁢                                                                                          R                                              f                        ⁢                                                                                                  ⁢                        1                                                                                    R                                              i                        ⁢                                                                                                  ⁢                        1                                                                              ⁢                                      {                                          1                      +                                                                                                    R                                                          f                              ⁢                                                                                                                          ⁢                              3                                                                                                            R                                                          i                              ⁢                                                                                                                          ⁢                              3                                                                                                      ⁢                                                                              1                            -                                                          j                              ⁢                                                                                                                          ⁢                              ω                              ⁢                                                                                                                          ⁢                                                              C                                2                                                            ⁢                                                              R                                                                  i2                                  ⁢                                                                                                                                                                                                                                                                                  1                            +                                                          j                              ⁢                                                                                                                          ⁢                              ω                              ⁢                                                                                                                          ⁢                                                              C                                2                                                            ⁢                                                              R                                                                  i2                                  ⁢                                                                                                                                                                                                                                                                                                                  }                                    ⁢                                      (                                                                  V                        dv                                            +                                              V                        h                                                              )                                                  +                                  V                  h                                                                                                        =                            ⁢                                                                    -                    j                                    ⁢                                                                          ⁢                  ω                  ⁢                                                                          ⁢                                      C                    s                                    ⁢                                      R                                          f                      ⁢                                                                                          ⁢                      1                                                        ⁢                                      V                    dv                                                  -                                                      (                                          P                      +                      Qj                                        )                                    ⁢                                      V                    dv                                                  -                                                      (                                          P                      -                      1                      +                      Qj                                        )                                    ⁢                                      V                    h                                                                                                          (        4        )            Note that P is expressed by Equation (5) shown below. Q is expressed by Equation (6) shown below.
                    P        =                                            R                              f                ⁢                                                                  ⁢                1                                                    R                              i                ⁢                                                                  ⁢                1                                              +                                                    R                                  f                  ⁢                                                                          ⁢                  1                                                            R                                  i                  ⁢                                                                          ⁢                  1                                                      ⁢                                          R                                  f                  ⁢                                                                          ⁢                  3                                                            R                                  i                  ⁢                                                                          ⁢                  3                                                      ⁢                                          1                -                                                      ω                    2                                    ⁢                                      C                    2                    2                                    ⁢                                      R                                          i                      ⁢                                                                                          ⁢                      2                                        2                                                                              1                +                                                      ω                    2                                    ⁢                                      C                    2                    2                                    ⁢                                      R                                          i                      ⁢                                                                                          ⁢                      2                                        2                                                                                                          (        5        )                                Q        =                              ω            ⁢                                                  ⁢                          C              p                        ⁢                          R                              f                ⁢                                                                  ⁢                1                                              -                                                    R                                  f                  ⁢                                                                          ⁢                  1                                                            R                                  i                  ⁢                                                                          ⁢                  1                                                      ⁢                                          R                                  f                  ⁢                                                                          ⁢                  3                                                            R                                  i                  ⁢                                                                          ⁢                  3                                                      ⁢                                          2                ⁢                ω                ⁢                                                                  ⁢                                  C                  2                                ⁢                                  R                                      i                    ⁢                                                                                  ⁢                    2                                                                              1                +                                                      ω                    2                                    ⁢                                      C                    2                    2                                    ⁢                                      R                                          i                      ⁢                                                                                          ⁢                      2                                        2                                                                                                          (        6        )            
Therefore, the conditions “P=0” and “Q=0” can be achieved by adjusting the resistance value Ri2 of the variable resistor 54 and the resistance value Ri3 of the resistor 63 depending on the parasitic capacitance Cp. To measure the capacitance Cs of the capacity 30 to be measured, these resistance values Ri2 and Ri3 are adjusted before the capacity 30 to be measured is connected to the impedance detection circuit. Under these conditions, the resistance value Ri2 of the variable resistor 54 is expressed by Equation (7) shown below. The resistance value Ri3 of the resistor 63 is expressed by Equation (8) shown below.
                              R                      i            ⁢                                                  ⁢            2                          =                              1            +                                          1                +                                                      ω                    2                                    ⁢                                      C                    p                    2                                    ⁢                                      R                                          i                      ⁢                                                                                          ⁢                      3                                        2                                                                                                          ω              2                        ⁢                          C              2                        ⁢                          C              p                        ⁢                          R                              i                ⁢                                                                  ⁢                3                                                                        (        7        )                                          R                      f            ⁢                                                  ⁢            3                          =                              R                          i              ⁢                                                          ⁢              3                                ⁢                                    1              +                                                ω                  2                                ⁢                                  C                  p                  2                                ⁢                                  R                                      i                    ⁢                                                                                  ⁢                    1                                    2                                                                                        (        8        )            
As a result, the output Vout of the subtraction circuit 34 is expressed by Equation (9) shown below.Vout=−jωCsRf1Vdv+Vh  (9)Equation (9) indicates that the amplitude of the output Vout of the subtraction circuit 34 is in proportion to the capacitance Cs of the capacity 30 to be measured without being affected by the parasitic capacitance Cp.
As explained above, in the impedance detection circuit 300 shown in FIG. 4, it is possible to provide an output signal having a value that is not influenced by the parasitic capacitance Cp and is in proportion to the capacitance C, of the capacity 30 to be measured by adjusting the values of two variable resistors.